1. Field of Invention
The present invention relates to thin film processing at a single atomic layer precision for manufacturing of semiconductor devices. More particularly, this invention describes a process sequence that can be performed in one or more atomic layer/chemical vapor processing reactors to enable fabrication of microelectronic devices by employing thin film materials processing at atomic level precision. Furthermore, the process sequence as described herein is applicable to a variety of configurations for deep sub-micron devices such as thin film barrier deposition, gap fill for metallization and their subsequent planarization to form metal plugs, shallow trench isolation and inter-metal dielectric layers among others.
2. Description of the Related Art
Manufacturing of advanced integrated circuits (ICs) the microelectronic industry is accomplished through numerous and repetitive steps of deposition, patterning and etching of thin films on the surface of silicon wafer. An extremely complex, monolithic and three-dimensional structure with complex topography of variety of thin film materials such as semiconductors, insulators and metals is generated in an IC fabrication process.
The present trend in the IC fabrication, which is going to continue in to the foreseeable future, is to increase the wafer size and simultaneously decrease the individual device dimensions. As an example, the silicon wafer size has progressed in recent years from 150 mm to 200 mm and now to 300 mm. At the same time, the individual device dimension has decreased from 0.35 micron to 0.25 micron to 0.18 micron and further to 0.13 micron and 0.10 micron is on the horizon. Research and development for the upcoming devices with even smaller device dimension is being aggressively conducted. This trend demands extremely precise control of the critical process parameters such as film thickness, morphology and particularly conformal step coverage over complex topography and uniformity over an increasingly large area wafer surface.
In a typical monolithic IC fabrication process three dimensional device structures are fabricated on the surface of a silicon wafer through a repetitive sequence of deposition, patterning and etching of the layers in a precisely controlled manner. The etched portions of the wafer are filled with an appropriate conducting material on which the next layer is built by employing a similar process sequence. The process sequence that forms at the back-end of the microelectronic devices where all the active devices on the silicon wafer are connected by conducting wiring of copper is called dual damascene multi-level metallization scheme. Copper offers significant advantage due to its low electrical resistivity (<2.0 μΩ.cm) as compared to aluminum (˜4.5 μΩ.cm) in reducing resistance to electrical current.
However, copper tends to diffuse in to the adjacent layers of a dielectric material during operation of the circuit under the influence of electrical field and high temperatures generated due to large operational current densities. This can lead to short-circuiting two adjoining copper conductors and destruction of an active device. To avert this catastrophic end effect, but to retain the advantages copper can offer, it is clad in to a thin layer of diffusion resistant material called diffusion barrier.
In practice, to begin with a dielectric layer (preferably with low dielectric constant, hence called low-k) is deposited on to a planarized gate level dielectric layer. The planarized gate dielectric layer contains tungsten contact plugs that are normally filled by a chemical vapor deposition (CVD) process to establish electrical contact with the transistor. Next, the low-k dielectric layer is patterned and etched to open direct electrical contact to underlying tungsten plugs. Subsequently, a thin (˜50 Å or 5 nm) copper diffusion barrier layer is deposited into the etched features to arrest copper diffusion. The diffusion barrier also deposits on the top surface of the wafer. The materials commonly employed as diffusion barriers are nitrides of transition metals such W, Ta, Ti and may contain their admixtures with silicon or carbon with recent entrants such as Ru and RuO2. A thin copper seed layer, approximately 50-70 Å (5-7 nm), is deposited by sputtering or Physical Vapor Deposition (PVD). Subsequently, the as deposited silicon wafer is transferred in to an electrochemical cell, containing an aqueous solution of a copper salt as an electrolyte in which the silicon wafer, with a barrier layer and a copper seed layer, forms a cathode and a pure copper parallel plate forms an anode. An ensuing electrochemical reaction, under the application of electrical power, deposits copper metal in the etched portions on the wafer and fills them with copper metal. During the electrochemical deposition, however, copper also deposits on the top surface of the silicon wafer, between two adjacent contacts, which must be removed in order to obtain an exposed conducting pattern before the next level of low-k dielectric material is deposited. Thereafter, removal of excess copper on the top surface, along with the undesired diffusion barrier layer on the top surface of the wafer, is preferably achieved by a method called Chemical-Mechanical Polishing. Finally, a thin blanket layer of silicon nitride or silicon carbide (a few hundred Angstrom thin) is deposited on to the exposed copper plugs. These steps, beginning with the deposition of the low-k dielectric layer, are repeated desired number of times to build the multi-level metallization structure.
As an example of diffusion barrier deposition process, J. W. Klaus et al., in a paper published in the Journal of Electrochemical Society vol. 147, p. 1175-1181, March 2000; demonstrated deposition of tungsten nitride (W2N) thin films as a copper diffusion barrier by atomic layer deposition process employing tungsten hexafluoride (WF6) and ammonia (NH3) between 300-500° C.
Thin films of copper for seed layer have been deposited by various chemical processes. Chiang et al., described an ion-induced chemical vapor deposition process for the deposition of thin copper films employing Cu(hfac)TMVS [copper hexa-fluoro-acetylacetonate trimethyl vinyl silane] as a copper precursor in hydrogen plasma, in Journal of Vacuum Science and Technology A, vol. 15 No. 5, p. 2677-2686 (1997). Copper films deposited at room temperature by this method contained carbon and the resultant electrical resistivity was approx. 5 μΩ.cm which was substantially higher than that of pure copper (˜1.8 μΩ.cm). Lakshmanan et al., described a plasma assisted CVD process, to deposit low resistivity (˜2.2 μΩ.cm) copper thin films by employing Cu(hfac)2 [copper hexa-fluoro-acetylacetonate] in combination with hydrogen plasma below 190° C., in Journal of Electrochemical Society vol. 145, p. 694-700, February 1998. It was observed that purity of copper thin films was strongly dependent on the process pressure which affected H atom concentration in the gas phase and also process temperature that affected surface H atom concentration necessary to remove organic hfac group from the surface responsible for undesirable C, F and H impurities inclusion responsible for higher electrical resistivity of copper films. It is, however, noteworthy that at higher plasma power high-energy electrons and ions led to the decomposition of the copper precursor [Cu(hfac)2] in the gas phase. This resulted in to high resistivity copper films, most probably due to inclusion of elements or fractions containing fluorine, carbon and/or oxygen. Such a possibility can very well limit the envelope and scope of a plasma enhanced copper deposition process. Martensson et al., in the Journal of Electrochemical Society, vol. 145, p. 2926-2931, August 1998 described a low temperature (<250° C.) thermal atomic layer deposition process employing Cu(thd)2 [Cu(II)-2,2,6,6-trimethyl-3,5-heptanedionate] as a copper precursor with molecular hydrogen on a metal catalyzed substrate. The films deposited by this thermal ALD process were of high purity and also highly crystalline. The copper precursor [Cu(thd)2] employed in this process, however, is a low volatility solid with a significantly large molecular size which may hinder surface coverage of the substrate in an ALD process. Solanki et al., in the Electrochemical and Solid State Letters, vol. 3, No. 10, p. 479-480, 2000; described a copper ALD process employing Cu(hfac)2, X H2O [copper hexa-fluoro-acetylacetonate hydrate] with methanol, ethanol and formalin (37% formaldehyde) as reducing agents at 300° C. The resultant copper films showed excellent resistivity (˜1.78 μΩ.cm) at a thickness above 1200 Å. Soininen et al., in the U.S. Pat. No. 6,482,740 disclosed the deposition of metallic copper for interconnects in vias and trenches by reduction of copper oxide by various organic reagents such as alcohols, aldehydes and carboxylic acids. Both copper deposition processes described above employ aqueous solutions of these chemical reagents, which makes copper susceptible to oxidation. The aqueous process is also susceptible to difficulties encountered to transport viscous liquids into narrow sub-micron device features, which would tend to narrow further increase further with advancing device generations.
Kew-Chan Shim et al., described the results of a novel process of surface catalyzed deposition of copper in sub-micron features in the Journal of Electrochemical Society, volume 149, No. 2, page G109-G113, February 2002. The copper chemical precursor was hexafluoroacetylacetonate copper(1) trimethylvinylsilane [Cu(hfac)TMVS], which was combined with iodine, added by exposing the substrate to ethyl iodide [C2H5I] vapor prior to copper deposition, adsorbed on to the substrate surface. The substrate was silicon coated with 1.0 micron SiO2 on to which 45 nm thick layer of TaN and a 30 nm seed-layer of copper was sputter deposited. Copper deposition process temperature was 150° C. The process could fill the sub-micron trench (0.3 micron wide and 1.0 micron deep). The film growth and gap fill was a three step mechanism—in the first step conformal film of copper was deposited. In the second step the bottom of the trench was filled up and in the third step copper film grew laterally on the top surface of the substrate. Such a process, however, requires a base copper seed layer film to be deposited to initiate the copper deposition process. Moreover, this method of copper gap-fill does result into finite amount of copper deposition on the flat surface of the substrate which necessitates application of Chemical Mechanical Polishing (CMP) process to remove this and underlying copper diffusion barrier layer. The CMP process is beset with a variety of serious issues such as dishing, erosion etc. which are described by Wrschka et al., in the Journal of Electrochemical Society, volume 147, p. 706-712, February 2000.
Recently, Lim et al., in Nature Materials, vol. 2, pp. 749-754 November 2003, described self-limiting atomic layer deposition of several transition metals by thermal decomposition of N,N′-dialkylacetamidinato metal complexes of copper and cobalt, among other transition metals, in molecular hydrogen (H2) gas. Alkyl group in the copper metalorganic complex was isopropyl (i-C3H7). The resultant copper complex was a dimeric solid [melting point=170° C., vapor pressure=0.05 Torr at 70° C.] which reacted with H2 gas at 280° C., to deposit conformal copper films in a 10:1 aspect ratio feature. Apart from low volatility and potentially high cost and complexity of the copper chemical precursor molecule, the copper ALD process described above operates at higher temperature for the tolerance of delicate low-k dielectric materials.
ALD process of by reduction of cuprous chloride (CuCl) by molecular H2 between the temperatures of 300-350° C. was published by Martensson et al. in Chemical Vapor Deposition, volume 3, No. 1, p. 45-50 (1997). CuCl is a low volatility solid [m. p. ˜350° C.], however, it is a simple precursor molecule that is rather inexpensive in comparison with a variety of organometallic precursors evaluated so far. Also, it is a highly desirable precursor due to its straightforward and potentially clean reduction to metallic copper with hydrogen through hydrochloric acid (HCl) gas as a by-product and has significant potential to deposit high purity copper films. Moreover, its reaction with atomic hydrogen can potentially reduce the ALD reaction temperature significantly. However, being a low volatility solid, its large area distribution needs to be satisfactorily solved. In addition to this, atomic hydrogen tends to rapidly recombine on metal surfaces leading to its depletion in deep and narrow trenches. Thus in absence of an efficient mechanism to transport atomic hydrogen effectively and in sufficient quantities within etched features over the entire substrate surface, it would be difficult to realize an effective copper ALD process from CuCl and atomic hydrogen.
The copper chemical precursors employed in the copper deposition processes described above are low volatility and large organometallic molecules that are generally expensive. Moreover, their vapor phase dissociation, by application either of heat or plasma, is seldom clean and it tends to incorporate undesirable impurities such as carbon, fluorine and others that adversely affect the purity, resistivity and also adhesion of the resultant copper layer to the underlying diffusion barrier. In absence of a viable copper deposition process, the overall process sequence described above to obtain filled copper plugs lined with a diffusion barrier thus entails three different methods of processing namely: (a) physical vapor deposition or sputtering to deposit seed copper layer on top of the diffusion barrier layer (b) electrochemical copper deposition and (c) chemical-mechanical (or chemo-electro-mechanical) removal of copper. In a multilevel metallization structure each of these steps must be sequentially performed in a dedicated equipment once for each level of metallization. However the approach as outlined above has a number of serious pitfalls:                (a) Inadequate step coverage by sputtering of barrier in small vias and trenches: As the critical device dimensions reduce with each advancing device generation, the vias and trenches are becoming increasingly smaller from 0.13 to 0.10 micron and even below while aspect ratio is steadily increasing. Sputtering (PVD) being a line of sight process leads to inadequate deposition of thin film material on the side-walls of the dielectrics. As a result, conformality of barrier deposition by this method is becoming increasingly inadequate. This has led to significant and adverse impact on the quality of copper seed layer and subsequent copper gap fill process extending into the overall device quality.        (b) Poor conformality and discontinuity of copper seed layer by sputtering: Thin copper seed layer as sputtered on the underlying diffusion barrier also shows inadequate degree of conformal deposition and at times spatial discontinuity and non-uniformities over the contours and surfaces of the structures. However, any discontinuity in this layer has serious consequences for the next step of electrochemical copper deposition which requires a physically continuous copper layer. Thus reliability and quality of the device in terms of important functional parameters such as electromigration resistant can be seriously compromised if this step is not performed satisfactorily.        (c) Corrosion due to wet electrochemistry: This is a very serious issue that is under active investigation. The CMP or the other processes employed to remove copper such as dissolution of copper in acidic solutions, reverse anodic electro-dissolution of copper are fraught with corrosion of copper. This may be attributed to micro-quantities of trapped water within grains boundaries of copper. Copper is highly susceptible to oxidation when exposed to moist air at room temperature. Also, copper wiring in microcircuits during operation, as it conducts electricity, may heat up significantly. This may result in to undesirable scenarios: generation of high pressure localized steam that may lead to violent rupture of the interconnect structure or it may set up localized galvanic cells to initiate copper corrosion. Moreover, in-situ corrosion due photoelectrons has been an added issue. All these factors have a significant and adverse impact on the yield, reliability and overall stability of a copper metallization interconnect scheme being practiced currently.        (d) Dishing and erosion in CMP: During CMP the wafer surface is polished by rotating and pressing it against a flexible pad on to which an aqueous slurry containing a chemically active agent (chlorides of iron etc.) and an abrasive powder (such as ceria—CeO2) is spread. The copper layer to be polished is removed under a combined action of chemical reaction and mechanical force. The surface being polished usually results in to a dish shape within the feature with the material at the center of a feature being polished more as compared to the edge. Dishing is more pronounced in larger dimension features as compared to narrow features. Moreover, end point detection of the process is a complicated task which in practice leads to erosion and over polishing. Further to this, CMP may lead to micro-scratches, embedded undesirable solids and corrosive material residue on the surface. A thorough and proper clean with a deionized water is a highly essential to mitigate these issues.        (e) Defects in copper by CMP and electrochemistry: Various sources of defect generation in copper such as pin-holes, craters and volcanoes are associated with wet processes and CMP that impart adverse effects on the microstructure and overall quality of copper being laid down in the microcircuits.        (f) Process Waste Remediation: All the wet processes (CMP, Electrochemical Deposition, Copper Dissolution) in copper metallization use highly pure and deionized water in large quantities. Deionized water must be continuously supplied in large quantities and it must be treated properly to conform to the local, existing environmental regulations before it is discharged in to effluent stream. Moreover, large quantities of used chemical slurry must be contained and its remediation must be carried out according to guidelines. This adds to the expenses and can be a substantial part of the final cost and operation.        (g) Cost of multiple tools and spare hardware and process consumables: The metallization scheme, as outlined above, has three distinct process steps that require a separate process module each. It thus entails substantial operating costs to the owner per tool in terms of expensive fab floor space, tool operation, maintenance, and process chemical consumption and also cost of each tool maintenance and process consumables. All these factors add to the cost-of-ownership significantly.        
In summary, the existing multiple process equipment and their operation suffer from various drawbacks and issues that adversely impinge on the cost, reliability and device yield. Moreover, the current equipment as described above, may not be easily extendible for the upcoming smaller device dimensions. Thus, there is a clear and urgent need for vapor phase processes for deposition, gap fill and top layer removal and related equipment to provide the following:                Perfectly conformal step coverage and process for the diffusion barrier layer,        Seamless and high speed copper/conductor vapor phase deposition process to completely fill vias and trenches (the contacts) without void, key-hole, seam or other defects with excellent adhesion and electro-migration resistance,        High speed vapor phase removal process for the excess top layer of copper/conductor material deposited during the gap fill,        Precision and vapor phase removal of the diffusion barrier process to expose the underlying dielectric layer,        Extendibility of the process and equipment for processing of increasingly larger diameter wafers with continuously decreasing device dimensions below 0.10 micron,        Improved uniformity and excellent thickness control across the wafer with high degree of process stability and repeatability        
A method of filling a gap structure in an electronic device, employing vapor phase chemistries, was disclosed in the U.S. Pat. No. 6,635,965 wherein the inventors supplied the reactive gases alternately in a pulse mode to the substrate with features, placed on a first station in a multi-substrate processing chamber, to obtain near perfect step coverage of the feature. During the pulse deposition process one or more monolayers may be deposited on the etched feature. Subsequently, the substrate was transferred to the high-rate Chemical Vapor Deposition (CVD) station to fill the gap structure completely. In the U.S. Pat. No. 6,551,929; a method of forming gap-filled structures on a substrate involving two separate process chambers was disclosed. In this gap-structure filling method a patterned substrate, was exposed to alternating flows of reactive gases in the first processing chamber to form a nucleating layer. Next the substrate was transferred to the second processing chamber wherein the patterned gap-structures were filled by employing a high-rate CVD process. In both the inventions described above, two distinct substrate processing reactors were required to completely fill the gap structure on the substrate wafer.
Lopatin et al., in the U.S. Pat. No. 6,368,954 described the application of ALD in the fabrication process of copper interconnects. In this invention, a pre-seed layer and a thicker seed layer, both of copper, follow deposition of the diffusion barrier layer. The inventors described the process of formation of diffusion barrier layer and subsequent copper seed layer, both by ALD processes in the same reactor. The inventors also recommend that reactor be purged with N2 between two ALD processes for almost 15 minutes to an hour. The chemical composition of diffusion barrier and copper are substantially different and to avoid cross contamination, it is highly advisable to perform respective chemical processes for different thin film materials in dedicated reactors. Also, long durations of dry nitrogen purge can slow the overall process sequence and make it uneconomical. The invention states a two step copper deposition process—pre seed layer and seed layer. The inventors also state that the copper seed layer can be substantially thicker than the barrier layer and for very narrow trenches it may serve to form the interconnect itself and no further electrolytic deposition may be needed. However, this approach of interconnect fabrication can be practical only in case of extremely narrow features where the rate of deposition of existing ALD processes is sufficient to offer economical throughput. The current ALD equipment, however, is woefully inadequate to process thicker films. Furthermore, electrochemical deposition (ECD) to fill the etched vias and trenches with copper and CMP to remove the excess copper and diffusion barrier on the top surface are both necessary.
Nguyen et al., in the U.S. Pat. No. 6,284,052 described removal of a copper layer deposited on the internal reactor surfaces such as heated wafer chuck, by oxidizing it first with oxygen plasma and then reacting it in-situ with a liquid chelating agent such as 1,1,1,5,5,5-Hexafluoro-2,4 pentanedione (H+ hfac) to form a volatile solid compound copper (II)(hfac)2 that is removed from the reactor under the action of vacuum and elevated temperature. In the chamber clean process employed herein, active oxygen plasma is used to fully oxidize deposited metallic copper in to copper oxide which limits the nature of the process sequence to a two step process because the chelating agent, which is usually an organometallic compound, and the oxygen plasma cannot be simultaneously present in the chamber to prevent its decomposition. Moreover, the process chemistry is limited to copper oxide only. The process of removal of deposited copper on the internal surfaces of the chamber is carried out only when the substrate wafer is removed from within the process chamber.
Andricacos in the Electrochemical Society Interface, p. 32-37, Spring 1999 issue described filling of sub-micron features for damascene metallization in by copper electroplating through three distinct processes, described in detail later, such as: (a) anti-conformal (b) conformal and (c) super-filling. An anti-conformal filling process with a non-uniform deposition on the side walls invariably led to a void in the center of the feature whereas a perfectly conformal filling process with uniform deposition on the side walls and also the bottom of the feature resulted into a seam at the middle which is an undesirable defect and thus cannot be satisfactorily employed for the gap-fill purpose. However, gap-fill through a super-filling process only, in which a higher amount of film is deposited at the bottom of the feature as compared to the side-walls, led to complete and defect free filling of the gap-structure found to be the most desirable process. Thus a conformal and an anti-conformal filling of a sub-micron feature were both shown to be highly defect-prone. Also, during an etch back process, employed for removal of excess deposition on the top surface, a defective filling of the feature can either begin to open up rapidly or be filled with the reactive fluids employed in the excess material removal process thus leading to full destruction of a highly critical void-free gap-filled structure required for high quality device fabrication.
In view of stringent processing demands and considerable difficulties being encountered listed above, atomic layer chemical vapor deposition (or ALD) with its extremely precise process control is the most suitable technique that can be employed effectively to obtain a desired solution. ALD is a simple variant of the industry prevalent technique of Chemical Vapor Deposition. ALD was invented in Finland in late 70s to deposit thin and uniform films of compound semiconductors such as Zinc Sulfide as described in the U.S. Pat. No. 4,058,430 by Suntola et al. There are several attributes of ALD that make it an extremely attractive and highly desirable technique for its application to the microelectronic device fabrication industry. ALD is a flux independent technique based on the well-known principle of monolayer formation by chemisorption, which is inherently self-limiting. ALD process is also relatively temperature uniformity insensitive. In a typical ALD sequence two highly reactive gases are injected sequentially on the substrate interspersed by an inert gas to sweep away excess reactants. A monolayer of the solid film is formed in each cycle and reaction by-products are swept away. The desired film is thickness is built by simply repeating the complete reaction sequence. The most desirable attribute of ALD is its ability to offer atomically uniform, perfectly conformal and area independent thin film coatings in high aspect ratio deep sub-micron geometries. With continuously decreasing device dimensions, such features in ALD make the application of ALD highly suitable and desirable for upcoming device generations and for larger diameter wafers. An excellent description of the fundamentals and applications of ALD and the progress it has made so far is offered in a review article written by T. Suntola titled Atomic Layer Epitaxy in the Handbook of Thin Film Process Technology, Part B 1.5, p. 1-17, IOP Publishing Limited, 1995, which is included herein as a reference.
In a typical ALD process, however, the rate of deposition is fixed and it is solely dependent upon the speed of completion of a single ALD sequence, which is generally 1 to 2 Å/cycle depending upon the thickness of the monolayer. For ALD to become acceptable to the microelectronic device fabrication industry it must offer competitive throughput. Hence, it is imperative to complete one ALD sequence comprising of four gas pulses in as short time as possible. Also, with the introduction of temperature sensitive low-k dielectric materials, higher process temperatures have become unacceptable. This has led to development of radical assisted ALD processes and reactor design as described in the U.S. Pat. No. 6,342,277 and plasma assisted ALD process and reactor design in the U.S. Pat. No. 6,416,822.
The ALD process, however, is significantly slower as compared to a CVD process that can operate at a rate of several hundreds of Ångstrom/minute. Such an operational handicap can very well lead to restricting application of ALD to only a few tens of Å thin films e.g., diffusion barriers or gate dielectrics. An ALD reactor that can operate as a high-rate CVD reactor is thus necessary to achieve desired process simplification. As an example, a flexible high-speed Atomic Layer Processing reactor which can also be operated as a high rate chemical vapor deposition reactor is described in detail in the U.S. Pat. No. 6,812,157. Its plasma enhanced variant configuration and associated Plasma Enhanced Monolayer (PEM) processes are described in the U.S. patent application Ser. No. 10/865,111 and apparatus and methods for in-situ chemical precursor generation for vapor phase processes as described in the U.S. patent application Ser. No. 10/975,169; which are relevant to the present invention and are included herein by way of reference.
It is thus apparent to an individual skilled in the art that a flexible and high-speed atomic layer processing reactor employed to facilitate processing of various thin films is a generic one in nature and is thus not limited by the reaction chemistry of deposition or etching or surface modification of any desired film material. Therefore, a high-speed and flexible ALD reactor has a secondary purpose to process, using one or more embodiments described herein, a variety of thin films of metals, semiconductors and insulators and suitable combinations thereof with atomic level precision on a substrate under suitable process conditions. To an individual skilled in the art, the objectives and advantages of the present invention will soon become apparent from the summary, detail description of the invention and specific embodiments described herein. It should be understood, however, that the detail description of the invention and specific embodiments are given by way of illustration only, since various modifications and combinations of specific features of one or more embodiments are well within the scope and spirit of the present invention. In summary, the foregoing description indicates that there is a clear and urgent need to devise a scheme that will simplify gap-filling process sequence, improve the quality of thin films and reduce process complexity and enhance the device yield while critical device dimensions are continuously reduced.